The present invention relates to differential amplifiers and, more particularly, to offset adjustment in MOS differential amplifiers.
MOS integrated circuit differential amplifiers typically include a pair of source-coupled transistors with current sources connected to the drains of the source-coupled pair. Ideally, the sizes of the devices forming the differential amplifier (including the current sources) would be perfectly matched (i.e., identical in size, performance, etc.). However, in practice, the devices are not perfectly matched, resulting in an input offset. In some applications, this offset is undesirable. Some conventional methods to reduce the offset are to trim one or more devices to more closely match the devices. For example, one convention method to trim offset is to use a laser to alter the size of one or more devices in the differential amplifier. Laser trimming typically requires that the integrated circuit be powered on to determine the offset, then powered down to laser trim, and then powered on to verify the laser trimming sufficiently reduced the offset. Laser trimming may be repeated until the offset is within tolerance. Consequently, laser trimming is a relatively long process, which is undesirably in a typical production environment. In addition, the high energy of the laser trimming process can undesirably affect the performance of the integrated circuit by creating holes and electrons in the semiconductor material. Still further, trimming of resistors as in some conventional offset trimming processes may undesirably change other performance parameters in addition to offset.
In accordance with aspects of the present invention, a differential amplifier with adjustable offset is provided for a variety of applications (e.g., a comparator, bandgap voltage reference, operational amplifier, etc.). In one aspect of the present invention, the differential amplifier includes a differential pair, a controller, an offset adjuster and an output stage. In one embodiment, the differential pair and the output stage are standard implementations such as, for example, source-coupled PFETs and a folded-cascode output stage. However, in accordance with this aspect of the present invention, the offset adjuster includes transistors that can be selectively enabled to form a composite transistor that is connected in parallel with at least one transistor of the differential pair. That is, the offset adjuster can be selectively controlled to enable one or more transistors in the offset adjuster to, in effect, increase the size of one of the transistors of the differential pair. Using this aspect, the controller can reduce offset by causing the offset adjuster to increase the effective size of the appropriate transistor of the differential pair to compensate for device mismatch in the differential amplifier.
In another aspect of the present invention, the offset adjuster includes two sets of transistors, one set being connected in parallel with one transistor of the differential pair, and the other set being connected in parallel with the other transistor of the differential pair. Each set""s transistors have binary-weighted sizes (i.e., with the sizes being 1xc3x97, 2xc3x97, 4xc3x97, 8xc3x97 and so on). This aspect provides a simple system to implement a relatively wide range of effective sizes of either transistor of the differential pair with a relatively small quantization or granularity.
In yet another aspect of the present invention, the offset controller can be reconfigurable. For example, the controller can be implemented to include non-volatile memory to provide a binary-coded control signal to the offset adjuster. This aspect allows for re-adjustment of the offset compensation. For example, the offset compensation can be readjusted in response to changes in device parameters that might occur over time, or in response to different supply voltages, temperature, etc.